MOS 6502

The 6502 was designed primarily by the same engineering team that had designed the Motorola 6800. After quitting Motorola en masse, they quickly designed the 6501, a completely new processor that was pin-compatible with the 6800 (that is, it could be plugged into motherboards designed for the Motorola processor, although its instruction set was different). Motorola sued immediately, and although today the case would have been dismissed out of hand, MOS agreed to stop producing the 6501 and went back to the drawing board.

The result was the "lawsuit-compatible" 6502, which was by design unusable in a 6800 motherboard; Motorola, apparently no longer feeling threatened, did not object. However, this left MOS with the problem of getting new developers to try their processor, so engineer Chuck Peddle designed the KIM-1 single-board computer. Much to their surprise, the KIM-1 sold in huge numbers to hobbyists and tinkerers as well as to the engineers it was intended for. The related Rockwell AIM 65 control/training/development system also did well. Another roughly similar product was the Synertek SYM-1.

The 6502 was released in September 1975 at $25, when the 6800 and Intel 8080 were selling for $179. At first many people thought it was some sort of a scam, but shortly both Motorola and Intel had dropped their chips to $79. But instead of saving Intel and Motorola from the upstart MOS, the price reductions legitimized the 6502, which started selling by the hundreds.

One of the first "public" uses for the design was the Atari 2600 videogame console. The 2600 used an offshoot of the 6502 called the 6507, which had fewer pins and, as a result, could address only 8 KB of RAM. Millions of the Atari consoles would be sold, each with a MOS processor. The 6502 was next used in the Apple II family, and then appeared in various Commodore and Atari home computers, the BBC Micro family, and a huge number of other designs now lost to history such as Ohio Scientific. The 6510, a direct successor of the 6502 with a digital I/O port and a three-state bus, was the CPU utilized in the extremely popular Commodore 64 home computer. (Commodore's disk drive, the 1541, had a processor of its own—it too was a 6502.)

Another important use of the 6502 was in the Nintendo Famicom, a Japanese video game console. Its North American and European equivalent, the Nintendo Entertainment System, also used the processor. The 6502 used in the NES was a modified version, a partial system-on-a-chip, that lacked a binary-coded decimal mode but added 22 memory-mapped registers for sound generation, joypad reading, and sprite list DMA. Called 2A03 in NTSC consoles and 2A07 in PAL consoles (the difference being the clock divider ratio and a lookup table for audio sample rates), this processor was produced exclusively for Nintendo.

The efficient design of the 6502 also inspired the principal designers of the ARM RISC processor, and so the legacy of the 6502 may be said to transcend the original processor family. Its spirit lives on in the ARM design, which is used in several desktop computers as well as a plethora of handheld and other embedded systems and is sold as an IP block to be used in system-on-chip products.

[编辑] 描述

The 6502 is an 8-bit processor with a 16-bit address bus. The internal logic runs at the same speed as the external clock rate, but despite the slow clock speeds (typically in the neighborhood of 1 or 2 MHz), the 6502 was actually competitive with other CPUs using significantly faster clocks. This is partly due to a simplistic state machine implemented by combinatorial (clockless) logic to a greater extent than in many other designs; the two phase clock (supplying two syncronizations per cycle) can thereby control the whole machine-cycle directly. Like most simple CPUs of the era, the dynamic NMOS 6502 chip was not sequenced by a microcode ROM but nevertheless used a "small"* PLA for instruction decode and sequencing; and like most contemporary microprocessors, some execute/fetch overlap is done.

The low clock frequency moderated the speed requirement of memory and peripherals attached to the CPU as only about 50% of the clock cycle (this varied somewhat among chip versions) was available for memory access; critical at a time when (affordable) memory had access times in the range 450-250ns. The original NMOS 6502 was minimalisticly engineered and efficiently manufacured and therefore cheap; an important factor in getting design wins in the very price sensitive game console and home computer markets.

Like its precursor, the Motorola 6800 (but unlike Intel 8080 and similar microprocessors) the 6502 has very few registers**. Inside was one 8-bit accumulator register (A), two 8-bit index registers (X and Y), an 8-bit processor status register (P), an 8-bit stack pointer (S), and a 16-bit program counter (PC). The subroutine call/scratchpad stack's address space was hardwired to memory page $01, i.e. the address range $0100–$01FF (256–511). Software access to the stack was done via four implied addressing mode instructions whose function were to push or pop (pull) the accumulator or the processor status register. The same stack was also used for subroutine calls via the JSR (Jump to Subroutine) and RTS (Return from Subroutine) instructions.

The chip used the index and stack registers effectively with several addressing modes, including a fast "direct page" or "zero page" mode that accessed memory locations from address 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the second byte of the address) – code for the 6502 used the zero page much as code for other processors would have used registers. In most 6502-based microcomputers with an operating system, the OS itself used almost the entire zero page, leaving perhaps a handful of locations for the user.

Addressing modes also included implied (1 byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Absolute mode was a general-purpose mode. Branch instructions uses a signed 8-bit offset to modify the program counter as it would appear if the branch were not taken (i.e. two bytes past the branch instruction itself); the numerical range -128..127 therefore translates to 126 bytes backwards and 129 bytes forward from the branch instruction. Accumulator mode used the accumulator as an effective address, and did not need any operand data. Immediate mode used an 8-bit literal operand.

The indirect modes were useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register was added to a 16-bit base address in zero page, located by a single byte following the opcode; incrementing Y in order to walk the array (byte wise) took only two additional cycles. The Y register was thus an index register in a true sense, and the 6502's specifications, saying 8-bit index registers***, may be taken literally; it is about 8-bit indexing, not 8-bit addressing. With the less frequently used "(indirect,x)" mode the effective address for the operation was found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acted as a set of 128 additional (though very slow) address registers.

See the Hello world! article for a simple but characteristic example of 6502 assembly language.

* About 15% of the chip area actually!

** The 6800 was designed around 1973 at a time when (small bipolar) memories was relatively fast. It therefore made sense to use RAM instead of wasting expensive NMOS chip area on CPU-registers (then a significant part of the CPU)

*** This is where the 6502 differs most from the Motorola 6800, which has one 16 bits address/index register instead of two eight bits index registers.

[编辑] 見仁見智的功效特點

• 6502s are almost notorious for having a variety of undocumented instructions, which vary from one chip manufacturer to the next. The 6502's instruction decoding is implemented in a hardwired logic array (similar to a programmable logic array) which is only defined for 151 of the 256 available opcodes. The remaining 105 trigger strange and hard-to-predict actions (like crashing the processor immediately; performing several valid instructions at once; or as far as has been discovered simply doing nothing at all). All of the undefined opcodes were eventually replaced by NOP instructions in the subsequent 65C02 CMOS version (although with varying byte sizes and execution times).

• The 6502's memory indirect jump instruction, JMP (<address low-word>), was broken. If <address low-word> was hex xxFF (i.e. any word ending in FF), the processor would not jump to the address stored in xxFF and xxFF+1, but rather the one in xxFF and xx00. The 6510 did not fix this bug, nor was it fixed in any of the other NMOS versions of the 6502 such as the 8502 and the 2A03. The CMOS 65C02 fixed it, as did various of the CMOS derivatives.

• Simultaneous appearance of NMI (non-maskable) and IRQ (maskable) interrupts caused the latter to be ignored.

• Three of the status flags (N - negative, V - overflow and Z - zero) were invalid after performing arithmetic operation in BCD mode. This was also fixed in CMOS derivatives.

[编辑] 6502的16位元衍生版

Synertek published a data sheet and application notes on the SY6516, a 16-bit derivative of the 6502, but the part was never introduced.

The Western Design Center designed and produced the 65816 processor, a 16-bit successor to the 65C02 as well as a hybrid offshoot called the 65802 which was a 65816 with a 64 KB address space in a 65(C)02 pin-compatible package.

Mitsubishi (now Renesas Technology) made a line of 16-bit microcontrollers with an architecture very similar to the 65816, though it was not 100% compatible.

[编辑] 執行加速

Many users of 1 MHz 6502-based systems soon wished their computers could go faster. A number of companies sold replacement hardware to speed up those systems. Generally, 6502 system accelerators were based on:

• 6502 or 65C02 chips running at a faster clock rate
• 65C816 chips in 6502 emulation mode, running at a much faster clock rate (up to 20 MHz)
• 4 MHz and 8 MHz Zip Chip processors, made by Zip Technology, and 10 MHz Rocket Chips, made by Bits and Pieces, all using onboard cache RAM and proprietary glue logic to speed up processing while remaining compatible with a 1 MHz motherboard. Zip Technology's patent #4,794,523 eventually forced Bits and Pieces to cease manufacturing of the Rocket Chip.

[编辑] 6502的瑣碎關連

• In the science fiction movie The Terminator (1984), starring Arnold Schwarzenegger, the audience at one point is treated to a view through the T-800 Model-101 robot character's eye/camera display with some 6502 assembly/machine code program fragments scrolling down the screen. Also shown is the output from a run of an Apple II checksum program called KEY PERFECT 4.0, published in Nibble magazine.

• Bender, a fictional android "industrial robot" manufactured in 2998 AD, and a main character in the animated TV series Futurama, was revealed to have a 6502 as his "brain", in the episode "Fry and the Slurm Factory."

• Even today, 31 years after the 6502's introduction, some Universities, including the University of Tasmania, the University of Applied Sciences in Cologne, Germany, and Hull University still use the processor to teach assembly language and computer architecture.